The Shift from Physical Dimensions to Performance Equivalence in Semiconductor Process Nodes

From a “Tiny Faucet” to a Paradigm Shift

The most fundamental component in a chip is the transistor. A useful analogy is to think of a transistor as a miniature faucet: current flows from the source terminal to the drain terminal, while the “gate” acts as the valve that controls the flow. The length of the gate directly determines both switching speed and power consumption—a shorter gate means a shorter path for current from source to drain, faster switching, and lower energy consumed per switch.

Driven by this intuitive physics, chip engineers for decades pursued a clear objective: make the gate as short as possible. During this era, the nanometer figure was a literal physical measurement. Under a microscope, you could measure the gate length directly—a node labeled 45 nanometers was indeed 45 nanometers. Because this number had a strict correlation with performance gains, process nodes became the industry-standard, comparable metric for technological advancement.

Hitting the Physical Wall: The Squeeze of Leakage and Power

As processes advanced to smaller nodes, problems emerged. A shorter gate loses control over the channel current, exacerbating leakage. Specifically, “gate oxide leakage” occurs: even when the transistor is off, current still leaks through, preventing static power from dropping while dynamic performance fails to improve as expected. This is the first “physical wall” encountered in process scaling.

The root cause is that planar transistor structures had reached their control limits. The benefits of shorter gate lengths were partially offset by power losses from leakage, and the marginal returns of simply shrinking dimensions diminished sharply. What the industry needed was no longer “shorter gates,” but “stronger control.”

Structural Innovation: Standing the Channel Up

The solution came from a structural change: moving from planar transistors to FinFET (Fin Field-Effect Transistor). The core idea is to stand the channel upright, arranging it vertically like a fish fin. This increases the contact area between the gate and the channel from one side to multiple sides without increasing the chip’s footprint, significantly restoring control and suppressing leakage.

This structural shift also changed the evaluation framework. Gate length was no longer the sole determinant of performance: a 28-nanometer-wide gate in a FinFET structure outperforms a planar structure of the same width. The source of performance gains had partially moved from “size reduction” to “structural optimization.”

The Divergence of Node Numbers from Physical Dimensions

This created a problem. The industry and the public had long used process node numbers as a measure of chip advancement. If a manufacturer said, “our node number hasn’t changed, only the structure has,” the market would not accept it, and the chips would be hard to sell. Consequently, node naming gradually evolved into a “performance-equivalent” label: the number no longer corresponds strictly to a physical dimension but represents a level of performance comparable to a traditional node in terms of power, performance, and area trade-offs.

This transition led to several direct consequences:

• Naming decoupled from dimensions: Node numbers became marketing and communication symbols rather than measurable physical quantities.
• Cross-vendor comparisons became harder: products from different manufacturers labeled as the “same node” can differ significantly in actual performance and power; simple number comparisons are no longer sufficient.
• More evaluation dimensions: assessing a chip now requires examining structure, materials, packaging, and design co-optimization, rather than a single number.

Implications for Developers and Technology Selection

For developers and enterprise users, the practical meaning of this paradigm shift is straightforward: do not treat the process node number as the sole proxy for performance. When selecting hardware or evaluating options, a more reliable approach is to focus on measurable metrics, such as energy efficiency ratio, compute per unit area, and power behavior under typical workloads.

The following pseudocode illustrates this shift in evaluation thinking:

# Old approach: node number as the core metric
score = 1 / node_size
# New approach: comprehensive performance metrics
score = weighted_sum(
    perf_per_watt,        # energy efficiency
    compute_per_area,     # compute density
    leakage_at_idle,      # static power
    stability_under_load  # load stability
)

Conclusion

From “gate length defines the node” to “structure determines performance,” the evolution of semiconductor processes reveals a general pattern: when optimization along a single dimension approaches physical limits, system-level structural innovation replaces parameter fine-tuning as the primary driving force. The “distortion” of node numbers is not a regression; it is the inevitable result of evaluation frameworks catching up with technological complexity. Understanding this is essential for avoiding misleading impressions from surface-level numbers—and for focusing on the comprehensive metrics that truly determine real-world performance.