Two Key Advances in Premium Phones: Under-Display Biometrics and Wafer-Level Multi-Chip Packaging

As mobile computing power continues to rise, two development paths are shaping flagship devices: the front-facing design and on-device AI capability. One path focuses on the front structure, moving biometric sensors under the display to reduce cutouts and increase screen-to-body ratio. The other path focuses on internal packaging, shortening the distance between RAM and the processor to support local inference with lower latency. This article examines the engineering logic, implementation challenges, and design trade-offs behind both paths.

1. Under-Display Face ID: A Gradual Path from Notch to Punch-Hole

1.1 Three Stages of Structural Evolution

The evolution of the front-facing design does not happen all at once. It typically progresses through three stages:

1. Notched display stage: Sensors are concentrated in a single wide cutout. The structure is simple, but it takes up display area.
2. Punch-hole transition stage: Only the front camera retains a circular cutout, while other sensors move under the display.
3. Full under-display stage: The front camera also moves beneath the display, leaving the front surface close to a complete display area.

The second stage is the most realistic near-term target. Its engineering essence is “separation”: infrared projection and infrared reception components move below the display panel, while the visible-light front camera, which has the highest imaging quality requirements, remains in the screen cutout. If the front camera also moves under the display, additional problems such as light intake and diffraction must be solved.

1.2 Core Challenges for Under-Display Sensors

A display panel is a multi-layer structure containing pixel circuits and routing. Its main effects on under-display sensors include:

• Insufficient light transmittance: Higher pixel density leaves less room for infrared light to pass through. Local pixel density reduction or transparent routing areas may be required.
• Optical diffraction and scattering: Multiple thin-film layers in the panel can spread the light spot and reduce the contrast of projected patterns, affecting depth calculation accuracy.
• Display uniformity: Local transmissive areas may show brightness or color deviation, requiring pixel compensation algorithms.
• Thermal and stacking constraints: Moving sensor modules under the display intensifies competition for space with the battery and mainboard.

Common countermeasures include using special pixel arrangements in the sensor area, applying compensation algorithms to correct display differences, and optimizing the optical design of the projector to offset diffraction. These approaches share a common principle: trade physical-layer loss for computational-layer correction.

1.3 Security Boundaries for Biometric Recognition

For under-display biometrics to mature, the security level question must be addressed. The industry commonly uses liveness detection combined with depth-sensing methods such as structured light or time-of-flight. These systems project a known pattern and compare its deformation to determine whether a real face is present. Once sensors move under the display, the reduced signal-to-noise ratio directly affects false acceptance and false rejection rates. Hardening is therefore needed in the following areas:

• Projection power and exposure strategy: Dynamically adjust under limited light transmission conditions, balancing power consumption and accuracy.
• Multi-frame fusion: Accumulate multiple frames over time to improve signal-to-noise ratio.
• Template update mechanism: Gradually update biometric templates under controlled conditions to reduce interference from ambient light.

2. Two Structural Upgrades in the Camera System

2.1 Mechanical Aperture: Making Light Intake a Controllable Variable

Smartphone cameras have long used fixed apertures, with exposure adjustment relying mainly on shutter speed and ISO. With a mechanical aperture, the aperture value becomes an adjustable parameter, bringing two direct benefits:

• Suppressing overexposure in bright light: In high-illumination daytime scenes, the aperture can stop down to reduce light reaching the sensor and avoid highlight clipping.
• More flexible depth-of-field control: Aperture size affects depth of field, providing more physical means for bokeh and focusing strategies.

The engineering trade-offs are equally clear: aperture blades take up module volume and place higher demands on stabilization structure and module thickness. Blade actuation reliability, lifespan, and noise also require validation. As a result, this structure typically appears only on the large primary camera of flagship models, representing a trade of space for optical flexibility.

2.2 Sensor Upgrades: Rebalancing Dynamic Range

New image sensor designs generally focus on two directions: improving low-light sensitivity and suppressing daytime overexposure. These seem contradictory but actually rely on the same underlying capability: dynamic range. Common approaches include:

• Increasing pixel full-well capacity to improve highlight handling.
• Optimizing pixel structure and readout circuitry to reduce shadow noise.
• Using multi-gain readout and synthesis to fuse short-exposure and long-exposure information.

The synthesis logic can be expressed in illustrative pseudocode:

frame_short = capture(exposure=short)   # preserve highlight detail
frame_long  = capture(exposure=long)    # preserve shadow detail
hdr_frame   = merge(frame_short, frame_long, weights=local_contrast)

The combined value of a mechanical aperture and sensor upgrades is that the aperture provides physical light intake adjustment, while the sensor provides dynamic range headroom at the electronic level. Only by stacking both can imaging quality remain stable across different lighting conditions.

3. Wafer-Level Multi-Chip Packaging: Shortening the Memory Distance for On-Device AI

3.1 Motivation for Packaging Evolution

The core bottleneck for on-device AI is often not peak compute, but data movement. The physical distance between the processor and RAM determines access latency and bandwidth efficiency. In traditional designs, memory is packaged separately and connected through mainboard routing. Signal integrity constraints limit frequency scaling, and power consumption increases with long-distance transmission.

The basic idea of wafer-level multi-chip module packaging is to complete integration and interconnection of multiple dies at the wafer stage, then place memory closer to the processor. The benefits fall into three categories:

1. Lower access latency: Shorter physical distance means shorter signal paths.
2. Improved energy efficiency: Short-distance interconnects require less drive power.
3. Mainboard space savings: Higher integration frees up room for battery and thermal management.

3.2 Relationship to On-Device AI Capability

Local inference places demands on memory in two dimensions: capacity and bandwidth. Capacity determines whether model weights can reside locally. Bandwidth determines inference throughput. By moving memory closer to the processor, packaging enables more complex local models to run, reducing dependence on cloud round-trips. This lowers response latency and reduces data transmission costs and privacy exposure.

It is important to note that packaging only “shortens the distance.” It does not directly raise the performance ceiling of the memory itself. True on-device AI capability still depends on the coordination of chip compute, memory specifications, and the software stack. Engineering practice should focus on the balance of the overall data path:

on-device inference latency ≈ memory access latency × access count + compute latency

When access count is high, the benefit of shortening memory access latency is amplified. This is why packaging upgrades often prioritize AI workloads.

3.3 Design Constraints Introduced by Packaging Upgrades

High-integration packaging is not without cost. The main constraints include:

• Thermal management: Stacking multiple dies increases heat flux density, requiring redesigned heat spreading paths and thermal interface materials.
• Serviceability: Higher integration expands the impact of a single point of failure, raising requirements for testing and screening.
• Yield and cost: Wafer-level integration demands strict process consistency. Early yield ramp-up drives up cost.
• Supply chain coordination: Changes in packaging form affect mainboard layout, antenna design, and overall device structure, requiring early cross-team alignment.

4. Viewing Both Advances Together: A System-Level Space Reallocation Problem

Under-display sensors and advanced packaging may appear to belong to external design and internal structure respectively, but they are actually two sides of the same system-level challenge: reallocating resources within a constrained device footprint.

• Under-display designs give front cutout area back to the display, at the cost of increased optical and algorithmic complexity.
• Packaging designs give mainboard routing space to memory interconnects, at the cost of thermal and yield challenges.
• Mechanical apertures give internal module space to optical adjustment, at the cost of thickness and reliability validation.

All three point to the same conclusion: the evolution of premium mobile devices is no longer about single-component upgrades, but about multi-objective optimization across structure, algorithms, packaging, and thermals. For developers and system architects, the reusable methodology is:

1. Identify whether the bottleneck lies in “compute” or “data movement,” and prioritize solving data path problems.
2. Use algorithms to compensate for physical-layer losses, but evaluate the power and latency costs the algorithms themselves introduce.
3. When increasing integration, incorporate thermal and testability considerations into early design constraints.
4. Measure on-device AI capability end to end, rather than focusing on the specifications of a single component.

5. Summary

Under-display biometrics push the front design toward higher screen-to-body ratios. Mechanical apertures and sensor upgrades rebalance imaging quality across different lighting conditions. Wafer-level multi-chip packaging provides a shorter data path for on-device AI. Together, these advances define the next stage of premium mobile device evolution: trading structure for form factor, packaging for latency, and algorithms for optical headroom. Understanding the engineering logic behind these trade-offs is more valuable than memorizing specific parameters.