Equivalent Nanometers Explained: The Technical Truth Behind Chip Process Node Naming

It All Starts with One Word: “Equivalent”

When a chip is advertised as built on a “3nm process,” look closely and you may notice the word “equivalent” attached to the number. That qualifier is far more than marketing polish—it captures more than a decade of industry evolution: process node numbers stopped being the actual physical size of transistors long ago.

You could even call it a “naming game” that has run for over a decade across the entire supply chain—from foundries to chip designers to end-product advertising. This article isn’t aimed at any particular company. Instead, it goes back to the technology itself to answer three questions: how node naming evolved from real physical dimensions into marketing labels; what physical laws drove that shift; and how to rationally assess a chip’s process technology today.

The Golden Age: When Nanometers Meant Actual Dimensions

The Transistor: A Microscopic Switch

The most fundamental component in a chip is the transistor. Picture it as a voltage-controlled microscopic faucet:

• Current flows from the source at one end to the drain at the other;
• The gate in the middle acts like a valve, deciding whether the faucet is open or closed;
• A shorter gate means a shorter channel, a shorter path for charge to travel, faster switching, and lower dynamic power consumption.

For decades, then, the main storyline of process evolution was simple: keep shrinking the gate length.

When Names Strictly Matched Physics

In the 1970s, early commercial processors were built on process nodes around 10 micrometers (1 μm = 1,000 nm). By the 1990s the industry had moved to 350nm and 250nm, and through the early 2000s it progressed through 130nm, 90nm, 65nm, and 45nm.

During this era, the “node number” and the physical gate length were essentially the same thing. An engineer could measure the dimension on a wafer under a microscope—if a process was labeled 45nm, the gate really was 45nm. Every step down in the number brought simultaneous gains in performance, power, and density. This was the golden era described by classic Dennard scaling: dimensions shrank, voltage dropped, and power density stayed constant. Numbers were tightly coupled to benefits, and the whole industry placed enormous trust in the word “nanometer”—the historical root of the public habit of judging a chip’s sophistication by its process node.

Hitting the Physical Wall: The 28nm Turning Point

Scaling Runs Out of Room

As processes approached the 28nm node, conventional planar transistors ran into a physical wall. With ever-shorter gates, the electric fields from source and drain crept closer together, the gate’s electrostatic control over the channel weakened, and classic short-channel effects erupted:

• Subthreshold leakage surged, making standby power consumption uncontrollable;
• The gate oxide was thinned so aggressively that gate leakage became a serious problem;
• Boosting performance and cutting power began to directly conflict—simply shrinking the gate further delivered diminishing returns while side effects escalated.

The Structural Revolution: From Planar to 3D

The way out was not “shorter” but “more three-dimensional.” The industry took the flat, planar transistor and stood it upright, letting the channel rise from the silicon surface like a fin, wrapped by the gate on multiple sides. This is the FinFET (fin field-effect transistor).

The essence of the 3D structure is stronger electrostatic control: the gate-channel contact area expands from one side to three sides, so the gate “grips” the channel far more effectively. Leakage drops dramatically and switching behavior recovers. Later, the gate-all-around (GAA) structure pushed this evolution further, surrounding the channel on all sides for even tighter control.

The Naming System Breaks Down

The structure changed, but the measurement convention didn’t keep up. What determines performance expanded from a single “gate length” to a combination of 3D parameters—gate length, fin height, fin pitch, contact area, and more. Two processes both labeled “28nm” could behave completely differently depending on whether they used planar or 3D devices.

At this point, a vendor announcing “our node number is unchanged; we only upgraded the structure” would struggle in a market trained to read advancement from numbers—the chips simply wouldn’t sell. And so node numbers began to decouple from physical dimensions, gradually turning into marketing codes that represent “performance and density gains over the previous generation.”

“Equivalent Nanometers”: The Industry’s Post-Decoupling Consensus

Node Numbers Become Generation Labels

By the FinFET era, the industry had in practice admitted that node names no longer correspond to any single physical dimension. Today’s “7nm,” “5nm,” and “3nm” processes have real gate lengths and pitches far larger than their nominal numbers—these figures now function more like generational sequence numbers for a product line.

Nor do different manufacturers define the same number the same way: some key on transistor density, some on logic cell height, some on a blend of performance and power. Hence the rise of “equivalent.” The subtext of “equivalent Xnm” is usually: on a given dimension such as density or performance, roughly on par with the industry benchmark’s Xnm process. There is a real technical basis for this—when a new structure delivers a density gain comparable to a full generation of scaling, vendors may name the node accordingly—but at its core it remains a claim of comparability, not a statement of physical size.

Searching for a New Yardstick

Once the old coordinates fail, the industry naturally starts looking for new ones. Engineers increasingly focus on PPAC—the combined trade-off of Performance, Power, Area, and Cost. At the same time, attempts have emerged to redefine process evaluation with new “laws,” replacing increasingly distorted nanometer figures with quantifiable formulas.

The shared idea behind these efforts: stop arguing about “how many nanometers the number equals,” and instead answer “how much effective compute can be packed into a given area, and at what cost in power and money.” Whatever the specific formula, the direction is the same—pull evaluation from marketing narrative back to engineering fact, replacing a single long-distorted number with measurable metrics such as density and energy efficiency.

A Rational Way to Judge a Chip’s Process Technology

For developers, procurement decision-makers, and everyday users alike, the better move is to stop being led by node numbers and build a multi-dimensional judgment framework:

1. Transistor density: How many transistors fit per unit area is one of the hardest indicators of process sophistication. Public data such as logic cell density and SRAM cell area tells you far more than the node number does.
2. Energy efficiency: Performance per watt—power draw and performance output under identical workloads—is the metric that both mobile devices and data centers care about most. Measured results beat any nominal spec.
3. Real-world performance: What ultimately determines user experience is how the chip performs under real workloads—compile times, inference latency, memory bandwidth, sustained performance under thermal constraints—all of which can be verified through benchmarks.

Schematically, a rational evaluation framework looks like this:

process_advancement ≈ f(
    transistor_density,     # integration per unit area
    performance_per_watt,   # compute delivered per watt
    real_world_benchmarks,  # measured performance on real workloads
    yield_and_cost          # commercial viability
)

No single dimension—least of all the node number—is enough to support a conclusion on its own.

Conclusion

From 10 micrometers to “equivalent 3nm,” what changed is not just the numbers but the industry’s entire evaluation vocabulary. Node naming evolved from a strict statement of physical size into a post-revolution marketing code, driven by the 3D transition from planar transistors to FinFET and gate-all-around devices, and by the industry’s search for a new narrative once classic scaling laws ran out of steam.

The value of knowing this history is simple: the next time you see an “equivalent Xnm” claim, the questions to ask are not “how small is the number” but “how dense, how efficient, how strong in real tests.” The authority to evaluate a chip should rest on physical facts and engineering data—not on the default acceptance of a marketing figure.